--
-- VHDL Architecture codec_control.codec_control.arch
--
-- Created:
--          by - toban963.student (southfork-14.edu.isy.liu.se)
--          at - 10:39:18 10/04/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY codec_control IS
-- Declarations

END codec_control ;

--
ARCHITECTURE arch OF codec_control IS
SIGNAL temp_sign: std_logic_vector(0 TO 7);
BEGIN


  PROCESS(sys_clk)
  VARIABLE count: integer range 0 TO   
    BEGIN
      IF rising_edge(sys_clk) THEN
        IF I2C_DATA_fall = '1'

	IF count < 8 THEN
	  count := + 1;
	  i2c_sdat <= temp_sign(count);  
        ELSIF count = 8 THEN
	  IF i2c_sdat = '0' THEN
	    count := 0;
	    count2 := count2 + 1;
	  ELSE
	    sclk_on = '0';
	    count := 0;
	    count2 := 0;	
	  END IF;

	  IF count2 := 0 THEN
	    temp_sign <= "00110101"; -- address and write bit
	  ELSIF count2 = 1 THEN
	    temp_sign <= "????????"; -- register (15 downto 8)
	  ELSIF count2 = 2 THEN
	    temp_sign <= "????????"; -- data (7 downto 0)
	  END IF;
	END IF;
      END IF;

  END PROCESS;
    

  
  
  PROCESS(sys_clk)
    BEGIN
    IF rising_edge(sys_clk) THEN
      IF AUD_BCLK_last = AUD_BCLK THEN
        AUD_BCLK_last <= AUD_BCLK;
      ELSIF AUD_BCLK_last = '0' THEN
        AUD_BCLK_RISING <= '1';
      END IF;
    END IF;
  
  END PROCESS;
    
  
  
  PROCESS(sys_clk) -- Assuming left justified
    VARIABLE count: integer range 0 to 23;
    BEGIN
      IF rising_edge(sys_clk) THEN
        IF AUD_BCLK_RISING = '1' THEN
          AUD_BCLK_RISING <= '0';
      
          IF count = 23 THEN -- when bitclock has changed 24 times change read left/right data
            count := 0;
            AUD_ADCLRCK <= NOT AUD_ADCLRCK;
          ELSE
             count := count + 1;
          END IF;
      
          IF AUD_ADCLRCK = '1' THEN --reads bits when right channel selected
            right_aud_data(23 DOWNTO 1) <= right_aud_data(22 DOWNTO 0);
            right_aud_data(0) <= aud_adcdat;
          ELSIF AUD_ADCLRCK = '0' THEN --reads bits when left channel selected
            left_aud_data(23 DOWNTO 1) <= left_aud_data(22 DOWNTO 0);
            left_aud_data(0) <= aud_adcdat;
          END IF;
        END IF;
      END IF;
  END PROCESS;
  
END ARCHITECTURE arch;

